1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and particularly relates to a dynamic random access memory (which will be referred to as a "DRAM" hereinafter).
2. Description of the Background Art
In recent years, demands for semiconductor memory devices have been rapidly increased owing to rapid and wide spread of information equipments such as computers. Regarding a function, devices having a large-scale storage capacity and a high operation speed have been demanded. In view of this, technical development has been made for improving a density, a responsibility and a reliability of semiconductor memory devices.
The DRAM is a kind of semiconductor memory device allowing random input/output of storage information. The DRAM is generally formed of a memory cell array, which is a storage region storing large storage information, and a peripheral circuitry required for external input and output.
FIGS. 37A and 37B show a DRAM having conventional memory cells of a stacked type. Referring to FIGS. 37A and 37B, a p-type semiconductor substrate 1 is provided at its main surface with a p-type impurity region 3. A field insulating film 2 and p-type impurity regions 4a and 4b are formed on p-type impurity region 3. p-type impurity regions 4a and 4b are provided for controlling threshold voltages of transistors.
Lightly doped n-type impurity regions 5 which are spaced from each other are formed at the surface of p-type impurity region 4a. Lightly doped n-type impurity regions 5 and heavily doped n-type impurity regions 7 are formed at spaced portions of the surface of p-type impurity region 4b.
Gate electrodes 12 are formed on the main surface of semiconductor substrate 1 in the memory cell portion with gate insulating films 8b therebetween, respectively, and gate electrodes 12 are also formed on the main surface of semiconductor substrate 1 in the peripheral circuitry with gate insulating films 9 therebetween, respectively. Gate insulating films 8 and 9 are equal in thickness. Each gate electrode 12 is formed of a polycrystalline silicon film 10 and a WSi film 11.
A TEOS (Tetra Btyle Ortho Silicate) is formed on gate electrode 12, and a side wall insulating film 14 is formed on the side wall of gate electrode 12. Gate electrodes 12 are covered with an interlayer insulating film 15 extending through the memory cell portion and the peripheral circuitry. Contact holes 15a and 15b are formed in interlayer insulating film 15.
A bit line 16a having a portion located within contact hole 15a extends on interlayer insulating film 15, and an interconnection layer 16b having a portion located within contact hole 15b extends on interlayer insulating film 15. Bit line 16a and interconnection layer 16b are covered with an interlayer insulating film 17. Contact holes 17a which reach lightly doped n-type impurity regions 5, respectively, extend through interlayer insulating films 17 and 15.
Storage nodes 18 which have portions located within contact holes 17a, respectively, extend on interlayer insulating film 17. A surface of each storage node 18 is covered with a capacitor insulating film 19, over which a cell plate 20 is formed. Cell plate 20, capacitor insulating film 19 and storage node 18 form a capacitor 21.
Capacitors 21 and interlayer insulating film 17 are covered with an interlayer insulating film 22. The peripheral circuitry is provided with a contact hole 23a extending through interlayer insulating films 22 and 17, a contact hole 23b reaching corresponding gate electrode 12 and a contact hole 23c reaching heavily doped n-type impurity region 7. Metal interconnections 24b, 24c and 24d, which have portions located within contact holes 23a, 23b and 23c, respectively, extend on interlayer insulating film 22. In the memory cell portion, metal interconnections 24a are formed on interlayer insulating film 22.
In recent years, elements have been further miniaturized, and the thicknesses of gate insulating films 8b and 9 have been reduced. Particularly, a concentration of p-type impurity region 4a for controlling a threshold voltage of the transistor in the memory cell portion have been increased in accordance with the above reduction in thickness. Consequently, such a problem is becoming manifest that a leak current at a pn-junction (which will be merely referred to as a "junction leak current" hereinafter) increases.
According to the isolating structure of the trench type shown in FIGS. 37A and 37B, there is a tendency that a stress concentrates at the vicinity such as a region A and B of the periphery of field insulating film 2. In this case, the junction leak current cannot be suppressed sufficiently because the source/drain of the transistor in the memory cell portion are formed of only lightly doped n-type impurity region 5. Further, an etching damage is liable to occur at region A when side wall insulating film 14 is etched. This also becomes a cause of generation of the junction leak current. Such a junction leak current may destroy data stored in storage node 18.
Further, the foregoing increase in concentration of p-type impurity region 4a for the threshold voltage control causes disadvantageous increase in sheet resistance of lightly doped n-type impurity region 5.